The present invention relates to receiver architecture, in particular, high-speed receiver architecture.
In high-speed receiver circuits, data is sent from a transmit chip to a receiving chip on a printed circuit board. The data bits are sent as differential voltage signals, corresponding to binary symbols. The receiver circuit performs the function of clock and data recovery (CDR). It samples the data and also tracks the timing of the data with high precision.
High speed receiver circuits are useful for short chip-to-chip communications between two microprocessors (μp), a μp and memory, a μp and a graphics chip, etc. Standards for use of high speed receivers include HyperTransport, FB-DIMM, PCI Express, etc.
High speed receiver chips are also useful for backplane communication across longer distances. There are various standards of use for high speed receiver for backplane communication, including Fiberchannel, Ethernet, etc.
Two important factors to consider in comparing receiver circuits are area (mm2/Gbps) and power (mW/Gpbs). Current architectures for high speed receivers include a differential CML (“Current Mode Logic”) receiver. These receivers typically have an area of greater than 50000 μm2and require power of greater than 10 mW/Gpbs.